fpga开发-vivado FIFO IP核的使用

FIFO是先进先出的数据缓存器。起到跨时钟域的数据缓冲作用，一般在实际应用过程当中采用异步读写的方式，

选择的配置如下

封装IP核

module clk_wiz(

        input    resetn         ,
        input    clk_in1        ,

        output   clk_out1       ,
        output   clk_out2       ,
        output   clk_out3       ,
        output   clk_out4       ,
        output   locked         

    );

clk_wiz_1 clk_inst
   (
    // Clock out ports
    .clk_out1(clk_out1),     // output clk_out1
    .clk_out2(clk_out2),     // output clk_out2
    .clk_out3(clk_out3),     // output clk_out3
    .clk_out4(clk_out4),     // output clk_out4
    // Status and control signals
    .resetn(resetn), // input resetn
    .locked(locked),       // output locked
   // Clock in ports
    .clk_in1(clk_in1));      // input clk_in1

测试文件如下：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2024/03/12 16:51:42
// Design Name: 
// Module Name: sim_fifo
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module sim_fifo(

    );

reg          rst                        ;      
reg          wr_clk                     ;      
reg          rd_clk                     ;      
reg          [4 : 0] din                ;      
wire          wr_en                      ;      
wire          rd_en                      ;      
wire         [4 : 0] dout               ;
wire         full                       ;
wire         almost_full                ;
wire         wr_ack                     ;
wire         empty                      ;
wire         almost_empty               ;
wire         valid                      ;
wire         underflow                  ;
wire         [3 : 0] rd_data_count      ;
wire         [3 : 0] wr_data_count      ;
wire         wr_rst_busy                ;
wire         rd_rst_busy                ;


//读时钟
initial rd_clk = 1;
always#5 rd_clk = ~rd_clk;
 
//写时钟
initial wr_clk = 1;
always#25 wr_clk = ~wr_clk;
 
//读使能、写使能
assign wr_en = ((~rd_en) && (~full));
assign rd_en = ((~wr_en) && (~empty));
 
//写数据 
always @ ( posedge wr_clk ) begin
    if ( rst )
        din <= 5'd1;
    else if ( wr_en )
        din <= din + 1'b1;
end
 
initial begin
    rst = 1;
    #11;
    rst = 0;
 
end



fifo_top    fifo_top_inst(

                     .rst             (rst          )             ,
                     .wr_clk          (wr_clk       )             ,
                     .rd_clk          (rd_clk       )             ,
                     .din             (din          )             ,
                     .wr_en           (wr_en        )             ,
                     .rd_en           (rd_en        )             ,
                     .dout            (dout         )             ,
                     .full            (full         )            ,
                     .almost_full     (almost_full  )            ,
                     .wr_ack          (wr_ack       )            ,
                     .empty           (empty        )            ,
                     .almost_empty    (almost_empty )            ,
                     .valid           (valid        )            ,
                     .underflow       (underflow    )            ,
                     .rd_data_count   (rd_data_count)            ,
                     .wr_data_count   (wr_data_count)            ,
                     .wr_rst_busy     (wr_rst_busy  )            ,
                     .rd_rst_busy     (rd_rst_busy  )            

    );


endmodule

仿真结果如下：

收获：

使用了FIFO IP核，了解了FIFO各个引脚的含义，对IP核的设置有了一个基础的认知。